1. Field of the Invention
The present invention relates to a read/program potential generating circuit of an electrically programmable device, in particular, for use in a fuse circuit comprising, e.g. an E (electrical)-fuse element or an antifuse element.
2. Description of the Related Art
In the field of semiconductor memories, a redundancy technique for remedying a chip by replacing a defective cell with a redundant cell is well known. The redundancy technique is adopted for the purpose of enhancing a chip yield at the time of a die sort test.
However, with developments in miniaturization of devices and an increase in number of functions (i.e. reduction of circuit margin) in recent years, there is a tendency that the defect ratio of chips in tests after assembly increases more and more. The increase in defect ratio leads to a rise in product cost. Thus, in these years, there is a demand for remedying a chip with a defective cell once again by redundancy technology after a packaging step.
Under the circumstances, in order to make it possible to program the address (defective address) of a defective cell even after the packaging step, a program device of a fuse circuit for storing the defective address tends to be changed from a laser fuse to an electrically programmable electrical fuse (e.g. an E-fuse element or an antifuse element).
Around 1992, FPGA (Field Programmable Gate Array) makers began to develop products which permit replacement of a defective cell with a redundant cell even after a packaging step. This technique relates to a “memory scheme”, that is, a scheme in which a defective address is stored by using the same device as a memory device in a memory array. Consequently, such problems arise that in a memory-embedded logic LSI, for instance, adjustment in timing between a memory and a logic (gate array) becomes difficult, and an increase in operation speed is difficult due to an inter-logic delay. At present, after all, even such FPGA makers are now developing a fuse circuit using an electrical fuse element, in particular, an antifuse element.
The antifuse element refers to a fuse element composed of a capacitor. It has a logic reverse to the logic of an ordinary fuse element (e.g. a laser fuse element, E-fuse element, etc.), and so this is called “antifuse” element. For example, in the case of the ordinary fuse element, the initial state (non-fusion-cut state) is the conductive state. When the ordinary fuse element is blown and fusion-cut (“programmed”) by a laser beam or an excessive current, the fuse element is set in the non-conductive state. In the case of the antifuse element, the initial state (non-destruction state of insulation layer) is the non-conductive state. When the insulation layer is destroyed (“programmed”) by excessive voltage, the antifuse element is set in the conductive state.
An ONO (oxide/nitride/oxide) layer is known as an insulation layer of the antifuse element. This insulation layer may be replaced with a semiconductor layer of, e.g. amorphous silicon. Further, DRAM makers have published an antifuse element using a capacitor of a stacked memory cell, and an antifuse element using an inter-gate insulation layer (ONO) of an EEPROM memory cell.
In the meantime, as is shown in FIG. 1, in a general LSI, in order to perform a cell replacement operation using a redundancy circuit after assembly, programming for a program element 12 is effected using a high potential VBP generated by a high potential generating circuit (VBP generating circuit) 11.
In the circuit shown in FIG. 1, at a Power-ON time, in order to confirm the state (conductive state/non-conductive state) of the program element 12, a high potential VBP is generated by the high potential generating circuit (VBP generating circuit) 11. In addition, at a Program time, in order to effect programming for the program element 12, the high potential generating circuit (VBP generating circuit) 11 generates a high potential VBP. In short, the high potential VBP is generated by the high potential generating circuit 11 in each of the state confirmation operation of the program element at the Power-On time and the programming operation at the Program time.
No problem arises in the case of an LSI, such as a general DRAM, in which an access (program) operation for the program element 12 is performed by the manufacturer side alone. However, the following problems arise in the case of an LSI, such as a DRAM-embedded logic LSI, in which an access (program) operation for the program element 12 can also be performed by the user side.
A first problem is as follows. The feature that the program element 12 can be programmed by the user side is necessary for the user. In this case, it is desirable that a chip using a laser fuse and a chip using an electrically programmable program element be handled similarly. However, in the case of the latter chip, as shown in FIG. 1, the high potential VBP for programming, which is generated by the high potential generating circuit 11, is always applied to elements such as the program element and barrier transistor.
A second problem is as follows. In general, the potential used for an embedded LSI such as a memory-embedded logic LSI is set to be lower than the potential used for a general LSI such as a general memory. It is difficult to produce a potential necessary for programming from this low potential. To solve this problem as regards general LSIs, Patent Document 3 (see the list below), for instance, proposes a two-stage boost architecture using two-stage boost circuits, and Patent Document 4 proposes an architecture using a negative potential generating circuit. In these approaches, however, a plurality of this type of circuits need to be arranged in order to obtain a necessary negative drive power.
A third problem is as follows. Normally, in a general LSI, the high potential VBP is constantly generated during a time period from Power-On to Power-Off. On the other hand, the thickness of a gate insulation layer of a transistor used in the embedded LSI is smaller than the thickness of a gate insulation layer of a transistor used in the general LSI. Hence, in the embedded LSI, there is a danger that the transistor is damaged by the high voltage VBP, and this poses a problem with the reliability of the transistor.
Documents relating to the above-described “Related Art” are listed below:
Patent Document 1: Jpn. Pat. Appln. KOKAI Publication No. 2001-67893
Patent Document 2: Jpn. Pat. Appln. KOKAI Publication No. 2002-203901
Patent Document 3: U.S. Pat. No. 6,278,651
Patent Document 4: U.S. Pat. No. 6,333,667.